What is the difference between PHYSICAL ADDRESS & LOGICAL ADDRESS during memory addressing or accessing?

revathy

• May 27th, 2012

physical address :: is the real address stored in the system itself and this 48 bit flat address works in layer1 of osi model... logical address:: is the 32bit address assigned to each system in a ne...

Sankar

• May 14th, 2012

Physical address stored temporary in database But logical address it can store data in database in permanently.

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jaideepchoudhary

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• Mar 25th, 2012

Real mode is the mode where the base instruction set of 8086 microprocessor family can be executed , whereas in the Protected mode ,the instruction set with new and advanced instructions of the microp...

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Prakash

• Oct 21st, 2011

For gray 1 pixel = 1 byte.
for color 1 pixel = 3 byte;
64kbps =64 kilo bit per sec;
64kbps= 64/8 kilo byte per sec= 8000 byte per sec;
so 540 gray pixels, time=540/8000=0.067sec;
for color 540 pixels, time= 540*3/8000=0.202 sec;

vengat86

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• Aug 18th, 2009

In transmission its considered as download and upload
so, we have 64kbps 
Divide by 8 to get the download speed so its 8kbps ie 8192 bits per sec
Now consider the image its 540Bytes convert into bits its 540*1024 = 552960
So divide both 552960 / 8192 = 67.5 sec
i.e., 1 min 7 secs

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raval vikram

• Sep 16th, 2011

16 bit

karam_sodhi@yahoo.com

• Sep 11th, 2011

-128 to +127

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Maharasi.V

 Profile Answers by Maharasi.V Questions by Maharasi.V

• Aug 13th, 2010

If the input is 0, previous state is maintained and if the input is 1, toggling operation occurs.

Arun Segaran

• Nov 2nd, 2007

It becomes a T-flip flop

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muthumlk

 Profile Answers by muthumlk Questions by muthumlk

• Aug 4th, 2010

For an SR latch, if S is in ON state, the latch is set. So the o/p is 1 and the latch is in ON state.

Gopi

• Jun 1st, 2005

Latch state is in high state( ouput Q = 1).

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How much time does a serial link of 64 Kbps take to transmit a picture with 540 pixels.

japan_dave88

 Profile Answers by japan_dave88 Questions by japan_dave88

• Aug 20th, 2009

I would say that it also depends on length of the link as suppose Two devices named A and B are located 1000 kilometer far and we have link of 64kbps. Than when A will start sending first bit of ...

shreekanthss

 Profile Answers by shreekanthss Questions by shreekanthss

• Feb 2nd, 2009

Suppose a pixel is represented by 8 bits. Then total size=540*8=4320bitsIt takes 4320/64000=0.0675 seconds

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Arun Segaran

• Nov 2nd, 2007

Not?many?synthesis?tools?are?available?to?synthesize?a?asynchronous?design?at?RTL?

swatias

 Profile Answers by swatias Questions by swatias

• Jan 11th, 2007

To avoid race effects and deadlock effect, synchronous circuits are used

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reddy

• Oct 31st, 2007

The use of capacitor circuits instead of logical gates as in static RAMs demand the refreshing circuits.The charging and discharging of capacitors while storing bits could cause errors.

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yogeshforever

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• Aug 4th, 2007

DCE stannds for data communication end. In compouter? world? a modem is a DCE device.DTE stands for data terminal equipment. It serves as the originators and receptors of the digital communication.For more information refer to the "Introduction to Microprocessor" by "Shridhar and Ghosh"

bashwin.87

 Profile Answers by bashwin.87 Questions by bashwin.87

• Feb 12th, 2007

U can think DCE as a modem & DTE as a system

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rajeev kumar

• Feb 7th, 2007

Locality of reference means refering a particular area of memory while allocating variables.Whenever we allocate variables they are stored in a particular area this phenomenon is called locality of reference.

vijay

• Dec 14th, 2006

Definition of: locality of reference Also known as "locality in space" and "spatial locality," it refers to the fact that most instructions in a program are in routines that are executed over and over...

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swatias

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• Jan 11th, 2007

Mantisa  range = + 2 ^ 23 to - 2^23Exponent range = 127 to - 126so total number range will be +2^23 * 10^127 to - 2^23*10^-126

santos

• Aug 30th, 2006

-126

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sumanyaram

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• Dec 5th, 2006

Sorry it is +23 onesX(2^127) and -23onesX(2^127)i bit for sign so only 23 bits

sumanyaram

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• Dec 5th, 2006

mantissa=24 bits , exponent=8 bitsfirst consider the exponent,range is -128 to +127second consider the mantissa , max is all onesso ans is: 24 ones X (2^127) is the max positivenumber -2...

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sumanyaram

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• Dec 5th, 2006

Praveen is right,1101 is not a valid BCD number........

Danny John

• Aug 8th, 2006

Praveen is right. we are supposed to do exactly what he did. For verification convert them to decimal that is 9 + 4 =13 that is in BCD it is 0001 0011.

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sumanyaram

 Profile Answers by sumanyaram Questions by sumanyaram

• Dec 5th, 2006

5 flipflops r enough to divide the frequency by 32

S

• Aug 15th, 2006

32=2^5 => 5 bit longNumber divisible is 2*5=10 bit longQuotient & Remainder both are 5 bit eachso total 25 flip-flops at least (+ may be some other auxilliary register also)

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smokindesi

• Oct 9th, 2006

could be anywhere in memory. You can get the address from the location in IVT (assuming this subroutine is not chained) based on service number (i.e Interrupt no)location of address (i.e pointer)is available at 4*(interrupt serviced)

vikas s kulkarni

• Aug 3rd, 2005

It is stored in interrupt vector table

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Danny John

• Aug 8th, 2006

I think the output remains the same because it violates both setup time and hold time that is the input should remain constant for the setup time before the clock pulse and constant for the hold time after clock pulse provided it is edge triggered.

Ramachandran P.R

• Apr 30th, 2006

Ans is for positive edge triggerd flipflop out put:0 and for negative edge triggered output:1

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Danny John

• Aug 8th, 2006

512 adresses and 4 bit word. Hence 2048 bits.

bharti

• Jul 13th, 2006

Bytes or Bits ??

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Danny John

• Aug 8th, 2006

Since Y=C'BA'+CB'A+CBA on simplification yields Y=C'BA' + CANow it depends on the multiplexer we are using. If 8:1 MUX is used then just use A, B, C as select lines and the output of the truth table a...

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Ramachandran P.R

• Apr 30th, 2006

PLL stands Phase Locked Loop and it consists of phasedetctor,lowpassfilter,error amplifier,voltage controlled oscillator

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