Suppose that the D input of a flip flop changes from low to high in the middle of a clock pulse. Describe what happens if the flip flop is a positive edge triggered type?

This question is related to Cisco Interview
  • Interview Candidate
  • 3
  • 5081

Showing Answers 1 - 3 of 3 Answers

Gopi

  • Jun 1st, 2005
 

If it is edge triggered type, then nothing will impact on ouput during middle of a clock pulse. Flipflop wont consider the input changes in middle of a clock pulse for edge triggering case.

  Was this answer useful?  Yes

Ramachandran P.R

  • Apr 30th, 2006
 

Ans is for positive edge triggerd flipflop out put:0 and for negative edge triggered output:1

  Was this answer useful?  Yes

Danny John

  • Aug 8th, 2006
 

I think the output remains the same because it violates both setup time and hold time that is the input should remain constant for the setup time before the clock pulse and constant for the hold time after clock pulse provided it is edge triggered.

  Was this answer useful?  Yes

Give your answer:

If you think the above answer is not correct, Please select a reason and add your answer below.

 

Related Answered Questions

 

Related Open Questions